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王永纲
单位:近代物理系
地址:合肥,中国科技大学四系
邮编:230026
电话:+86-551-63606499
个人主页: http://dsxt.ustc.edu.cn/zj_js.asp?zzid=865
实验室介绍: http://realtimetech.ustc.edu.cn
 
个人简历 Personal resume
1987年毕业于中国科学技术大学近代物理系核电子学专业;1990年7月在核物理专业获得理学硕士学位,随后留校任教;于1997年12月获理学博士学位。主要从事核探测器及核信号处理电子学方面的研究工作。96年至98年参加中国科技大学与比利时布鲁塞尔自由大学(VUB)PET研究组的国际合作项目工作,研制了高性能的VUB-PET的数据获取和处理系统;99年3月至00年3月,在比利时VUB工作,继续从事基于APD阵列探测器的新型PET的读出电子学研制工作;00年3月至01年3月,在比利时IMEC微电子研究中心工作,从事无线通信方面的ASIC电路设计;2005年12月被聘为中国科学技术大学教授、博士生导师。
 
研究方向 Research direction
1、探测器读出电子学/大型数据获取系统
2、医学分子影像/3D成像/红外成像技术
3、神经网络/人工智能/算法硬件化
 
招生信息 Enrollment information
具有下列条件被优先考虑:
1.应届毕业生
2.有物理学学习背景
3.有电路设计或信号处理工作经历
 
论文专著 The monograph
1) A 3.9 ps Time-Interval RMS Precision Time-to-Digital Converter Using a Dual-Sampling Method in an UltraScale FPGA - IEEE Transactions on Nuclear Science - 2016 - Vol.63, No.5, Oct. 2016, pp261
2) A 4.2 ps Time-Interval RMS Resolution Time-to-Digital Converter Using a Bin Decimation Method in an UltraScale FPGA - IEEE Transactions on Nuclear Science - 2016 - Vol.63, No.5, Oct. 2016, pp263
3) A Flexible 32-Channel Time-to-Digital Converter implemented in a Xilinx Zynq-7000 Field Programmable Gate Array - Nuclear Instruments and Methods A - 2017 - 847(2017)61-66
4) A 128-Channel, 710 MS/s Throughput, and Less than 10 ps RMS Resolution Time-to-Digital Converter Implemented in a Kintex-7 FPGA - IEEE Transactions on Nuclear Science - 2015年6 - 2015年第三期
5) FPGA Based Electronics for PET Detector Modules with Neural Network Position Estimators - IEEE Transaction on Nuclear Science - 2011.2 - Vol.58, No.1, Feb. 2011. p34-4
6) Theory and implementation of a very high throughput true random number generator in field programmable gate array - Review of Scientific Instruments - 2016.4 - 87, 044704 (2016)
7) Preliminary Performance of a Continuous Crystal PET Detector with TODT Readout Scheme - RT2016 - 2016 -
8) 3D position estimation using an artificial neural network for a continuous scintillator PET detector - Phys. Med. Biol - 2013 - 58 (2013)
9) An FPGA-Based Real-Time Maximum Likelihood 3D Position Estimation for a Continuous Crystal PET Detector - IEEE Transactions on Nuclear Science - 201602 - Vol.63, No.1
10) Real time bunch-by-bunch luminosity monitor for BEPCII - IEEE International Instrumentation and Measurement - 2008 -
11) Electronics for Monolithic Scintillator PET Detector Modules Based on Neural Network Position Estimators - IEEE Nuclear Science Symposium and Medical Imaging - 2009 - Otc. 2009, Orlando,USA
12) A linear time-over-threshold digitizing scheme and its 64-channel DAQ prototype design on FPGA for a continuous crystal PET detector - IEEE Transactions on Nuclear Science - 2014 - Vol. 61, No.1
13) Self-Organizing Map Neural Network-Based Depth-of-Interaction Determination for Continuous Crystal PET Detectors - IEEE Transactions on Nuclear Science - 2015年6 - Vol.62, No3
14) A Combination of Multiple Channels of FPGA Based Time-to-Digital Converter for High Time Resolution - NSS-MIC2016 - 2016 -
15) FPGA based digital phase-coding quantum key distribution system - SCIENCE CHINA, Physics, Mechanics & Astronomy - 201512 - Vol. 58, No. 12
16) Improved Statistics Based Positioning Scheme for Continuous Thick Crystal PET Detectors - IEEE Transactions on Nuclear Science - 2013 - Vol. 60, No.3
17) A 256-channel Multi-phase Clock Sampling-Based Time-to-Digital Converter Implemented in a Kintex-7 FPGA - I2MTC2016 - 2016.5 - May 23-26, 2016, pp 429-433
18) Implementation of a High Throughput LDPC Codec in FPGA for QKD System - 13th IEEE International Conference on Solid-State - 2016 - Oct.25-28, 2016
19) Real-time compensation of phase drift for phase-encoded quantum key distribution systems - Chinese Science Bulletin - 2011.8 - Vol.56, No.22: 2305-2311
20) High performance data acquisition system for IRFPA testing - IEEE International Symposium on Circuit and system - 2008 -
21) Physical Properties of LYSO scintillator for NN-PET Detectors - BMEI'09 - 2009 -
22) A Nonlinearity Minimization-Oriented Resource-Saving Time-to-Digital Converter Implemented in a 28 nm Xilinx FPGA - IEEE Transactions on Nuclear Science - 201510 - Vol.62, No.5
23) A Novel Nuclear Pulse Digitizing Scheme Using Time over Dynamic Threshold - 2011 IEEE Nuclear Science Symposium and Medical Im - 2011.9 - NSS-MIC2011
24) An Analog Solution Generating the Dynamic Threshold for TODT Digitizing Scheme - 2012 IEEE NSS/MIC - 2012 - pp786-788, Anaheim, CA, USA
25) Design and Performance of a Data Acquisition System for VUB-PET - IEEE Transactions on Nuclear Science Vol48, 2001.2 - 2001 - 2001
26) High resolution multi-channel voltage reference generator for experiments on quantum-dot devices - ICEMI’2009 - 2009 -
27) Evaluation of Machine Learning Algorithms for Localization of Photons in Undivided Scintillator Blocks for PET Detectors - IEEE transactions on nuclear science - 2008 - Vol.55, No.3, June 2008
28) Realization of FPGA-based Packet Classification in Embedded System - I2MTC2009 - 2009 -
29) Performance study of neural network position estimation for the monolithic scitillator PET detcteor modules - 2010 Nuclear Science Symposium and Medical Imaging - 2010.1 - 2010.10
30) Depth of Interaction Estimation Using Artificial Neural Network for Continuous Crystal PET Detector - IEEE NSS-MIC2012 - 2012 - pp1260-1263, Anaheim, CA, USA
31) A High-Speed Quantum Key Distribution System Based on Faraday-Michelson Interferometers - 7th IEEE/International Conference - 201411 - on Advanced Infocomm Technolog
32) Spartan-6 FPGA Based 8-Channel Time-to-Digital Converters for TOF-PET Systems - 2015 IEEE NSS-MIC Conference record - 201511 - (NSS-MIC2015)
33) impact of instrumentation parameters on the performance of neural network based positioning algorithms for monolithic scintillator blocks - uclear Science Symposium Conference Record, 2007. - 2007 -
34) High Throughput Architecture for Packet Classifiaction Using FPGA - ACM/IEEE Symposium on Architectures for Networking - 2009.1 - Princeton, USA
35) Feasibility studies with PET detector modules based on an APD array and LSO(EI) - IEEE Nuclear Science Symposium Conference Vol1 - 2001 - 2001
36) Design of Packet Classification Co-processor with FPGA - International Conference on Embedded Systems ... - 2005 - 2005
 
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